Hybrid optoelectronic buffer using CMOS memory and optical interfaces for 10-Gbit/s asynchronous variable-length optical packets

A hybrid optoelectronic buffer consisting of a complementary metal-oxide-semiconductor (CMOS) memory and optical/optoelectronic interface devices is described. The interface devices: an all-optical serial-to-parallel converter (SPC), electrical-to-optical parallel-to-serial converter (PSC), and optical clock pulse-train generator (OCPTG) enable write-in/read-out of preamble-free asynchronous high-speed optical packets to/from CMOS memory, and consequently, flexible and highly functional processing of the packets with CMOS circuitry. A prototype hybrid optoelectronic buffer subsystem using a field programmable gate array (FPGA)-based memory and modules for the interface devices is developed and error-free write-in and read-out operation for 10-Gbit/s asynchronous variable-length optical packets is demonstrated.