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In the domain of digital control systems, significant phase delays stem from various factors, such as analog-to-digital conversion, finite sampling frequency values, algorithm computation time, and the digital pulsewidth modulator (DPWM). Typically, the delay introduced by DPWMs has a more substantial impact than the preceding factors. While numerous approaches have been proposed to mitigate or eliminate such delays, multisampling stands out as one of the most commonly employed methods. However, recent innovative architectures, particularly those based on the asymmetric dual-edge (ADE) carrier, have demonstrated that digital pulsewidth modulation (PWM) with zero phase delay, or even positive phase gain, can be effectively implemented. This suggests the possibility of further enhancing dynamic performance by increasing the number of samples per cycle. Unfortunately, the potential benefits of multisampling may be compromised by the operating point dependence issues inherent in ADE-DPWM. This article introduces a comprehensive architecture and a conclusive design approach for multisampling ADE-DPWM, facilitating the harnessing of multisampling benefits without encountering operating point issues. The experimental verification includes assessments of small-signal responses and robustness against operating point variations. Additional experimental tests are conducted to emphasize the improved dynamic performance compared to state-of-the-art trailing-triangle edge carrier-based modulators.

Multi-sampling Digital Pulse-width Modulator based on Asymmetric Dual-Edge Carrier