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The past decade has witnessed a tremendous reduction in the feature size from the deep-submicron to the advanced nano-scale CMOS devices. In nanoscale devices based high-speed systems, the budgeting of jitter due to supply fluctuations is one of the major performance bottlenecks while designing integrated circuits (ICs). In this paper, an accurate and efficient method to analyse power supply induced jitter (PSIJ) in CMOS N-stage inverters is developed using the estimation-by-inspection method. Based on the Indefinite Admittance Matrix, a reduced two-port network is developed for a multiple-input circuit, considering the presence of the supply/bulk/ground sources. The closed-form expressions of the PSIJ have been evaluated for a single and N-stages CMOS inverter chain. The expression is also valid for the PSIJ analysis at any intermediate stage of the N-stage chain. For validation purpose, the circuits are designed in a standard 28 nm CMOS technology with V<inline-formula><tex-math notation="LaTeX">$_\text{DD}$</tex-math></inline-formula> of 1 V. The analytical results are compared with the simulation and the experiments. The maximum mean percentage error for EDA simulation and experimentally measured results are 2.4&#x0025; and 13&#x0025;, respectively. The proposed analysis is compared with some of the existing PSIJ modelling techniques and shows a significant improvement in speed-up factor and error percentage.

Indefinite Admittance Matrix Based Modelling of PSIJ in Nano-Scale CMOS I/O Drivers