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56.2: Investigating the IGZO‐TFT Performances Under Gate‐bias Stress With and Without Light Illumination for 4k2k 65‐inch Displays
Author(s) -
Yeh BoLiang,
Lin ChunNan,
Tseng HsienKai,
Wu ChengChung,
Huang ChaoHung,
Chang ChiaMing,
Wu WenBin
Publication year - 2013
Publication title -
sid symposium digest of technical papers
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.351
H-Index - 44
eISSN - 2168-0159
pISSN - 0097-966X
DOI - 10.1002/j.2168-0159.2013.tb06330.x
Subject(s) - trapping , materials science , thin film transistor , optoelectronics , subthreshold conduction , hysteresis , stress (linguistics) , subthreshold slope , charge (physics) , threshold voltage , voltage , electrical engineering , transistor , condensed matter physics , nanotechnology , physics , ecology , layer (electronics) , biology , linguistics , philosophy , engineering , quantum mechanics
We demonstrate high resolution the IGZO‐TFT of 4k/2k 65‐inch panel in G6 glass. Two kinds of etch‐stopper (ES) treatment power were used IGZO‐TFT, i.e., low and high power treatment (LPT and HPT), respectively. We studied the electrical characteristics of IGZO‐devices with LPT and HPT, including subthreshold slope (SS), threshold voltage (V th ), mobility, hysteresis, and V t shift under positive and negative gate‐bias temperature stress (PBTS and NBTS) with and without light illumination, respectively. The IGZO‐TFT with HPT can be attributed to the dominant charge trapping located at GI/IGZO, IGZO/ES interface and in the IGZO film, whereas those with LPT are mainly due to charge trapping located at the GI/IGZO interface. Finally, the IGZO‐devices with LPT can simultaneously achieve low SS, Vt, and little hysteresis, and high mobility, as compared with those with HPT, moreover, those with LPT under PBTS with and without light illumination exhibited lower Vt change than those with HPT.

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