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In this work, we explore the applicability of cache occupancy attacks and theimplications of secured cache design rationales on such attacks. In particular,we show that one of the well-known cache randomization schemes, MIRAGE, toutedto be resilient against eviction-based attacks, amplifies the chances of cacheoccupancy attack, making it more vulnerable compared to contemporary designs.We leverage MIRAGE's global eviction property to demonstrate covert channelwith byte-level granularity, with far less cache occupancy requirement (just$10\%$ of LLC) than other schemes. For instance, ScatterCache (a randomisationscheme with lesser security guarantees than MIRAGE) and generic set-associativecaches require $40\%$ and $30\%$ cache occupancy, respectively, to exhibitcovert communication. Furthermore, we extend our attack vectors to includeside-channel, template-based fingerprinting of workloads in a cross-coresetting. We demonstrate the potency of such fingerprinting on both inhouse LLCsimulator as well as on SPEC2017 workloads on gem5. Finally, we pinpointimplementation inconsistencies in MIRAGE's publicly available gem5 artifactwhich motivates a re-evaluation of the performance statistics of MIRAGE withrespect to ScatterCache and baseline set-associative cache. We find MIRAGE, inreality, performs worse than what is previously reported in literature, aconcern that should be addressed in successor generations of secured caches.

On the Amplification of Cache Occupancy Attacks in Randomized Cache Architectures