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The deployment of AI models on low-power, real-time edge devices requiresaccelerators for which energy, latency, and area are all first-order concerns.There are many approaches to enabling deep neural networks (DNNs) in thisdomain, including pruning, quantization, compression, and binary neuralnetworks (BNNs), but with the emergence of the "extreme edge", there is now ademand for even more efficient models. In order to meet the constraints ofultra-low-energy devices, we propose ULEEN, a model architecture based onweightless neural networks. Weightless neural networks (WNNs) are a class ofneural model which use table lookups, not arithmetic, to perform computation.The elimination of energy-intensive arithmetic operations makes WNNstheoretically well suited for edge inference; however, they have historicallysuffered from poor accuracy and excessive memory usage. ULEEN incorporatesalgorithmic improvements and a novel training strategy inspired by BNNs to makesignificant strides in improving accuracy and reducing model size. We compareFPGA and ASIC implementations of an inference accelerator for ULEEN againstedge-optimized DNN and BNN devices. On a Xilinx Zynq Z-7045 FPGA, wedemonstrate classification on the MNIST dataset at 14.3 million inferences persecond (13 million inferences/Joule) with 0.21 $\mu$s latency and 96.2%accuracy, while Xilinx FINN achieves 12.3 million inferences per second (1.69million inferences/Joule) with 0.31 $\mu$s latency and 95.83% accuracy. In a45nm ASIC, we achieve 5.1 million inferences/Joule and 38.5 millioninferences/second at 98.46% accuracy, while a quantized Bit Fusion modelachieves 9230 inferences/Joule and 19,100 inferences/second at 99.35% accuracy.In our search for ever more efficient edge devices, ULEEN shows that WNNs aredeserving of consideration.

ULEEN: A Novel Architecture for Ultra Low-Energy Edge Neural Networks