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Over the years, the DRAM latency has not scaled proportionally with itsdensity due to the cost-centric mindset of the DRAM industry. Prior work hasshown that this shortcoming can be overcome by reducing the critical length ofDRAM access path. However, doing so decreases DRAM area-efficiency,exacerbating the latency-area tradeoffs for DRAM design. In this paper, we showthat reorganizing DRAM cell-arrays using the emerging monolithic 3D (M3D)integration technology can mitigate these fundamental latency-area tradeoffs.Based on our evaluation results for PARSEC benchmarks, our designed M3D DRAMcell-array organizations can yield up to 9.56% less latency, up to 4.96% lesspower consumption, and up to 21.21% less energy-delay product (EDP), with up to14% less DRAM die area, com-pared to the conventional 2D DDR4 DRAM.

Mitigating the Latency-Area Tradeoffs for DRAM Design with Coarse-Grained Monolithic 3D (M3D) Integration