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We present a tool flow and results for a model-based hardware design forFPGAs from Simulink descriptions which nicely integrates into existingenvironments. While current commercial tools do not exploit some high-leveloptimizations, we investigate the promising approach of using reusablesubcircuits for folding transformations to control embedded multiplier usageand to optimize logic block usage. We show that resource improvements of up to70% compared to the original model are possible, but it is also shown thatsubcircuit selection is a critical task. While our tool flow provides goodresults already, the investigation and optimization of subcircuit selection isclearly identified as an additional keypoint to extend high-level control onlow-level FPGA mapping properties.

Model-based Hardware Design for FPGAs using Folding Transformations based on Subcircuits