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Static Random Access memories are scaled down in order to improve overall density of the chip and hence to lower the power consumption of the system. So increased density but less power consumption optimises the overall system. For SRAM sense amplifiers which are important peripheral circuitry also need to be designed to optimize overall system. Scaling and process variations may change the sense amplifier characteristics which further results to the wrong decision. It has been observed that the threshold variation gives rise to the power and delay variations. A proposed model has been derived for simplified latch to model the effect of threshold variations. The output is observed under the various conditions of VDD and temperature to obtain the optimum value of sense delay, power consumption using 180nm technology mode. In this paper the power of the sense amplifier circuit is reduced upto 30μw with reduced delay.

An Energy-Efficient sense amplifier using 180nm for SRAM