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This paper proposes an improved branch predictor that reduces the number execution cycles of applications by selectively accessing a specific element in 4-way associative cache. When a branch instruction is fetched, the proposed branch predictor acquires a branch target address from the selected element in the cache by referring to MRU buffer. Branch prediction rate and application execution speed are considerably improved by increasing the number of BTAC entries in restricted power condition, when compared with that of previous branch predictor which accesses all elements. The effectiveness of the proposed dynamic branch predictor is verified by executing benchmark applications on the core simulator. Experimental results show that number of execution cycles decreases by an average of 10.1%, while power consumption increases an average of 7.4%, when compared to that of a core without a dynamic branch predictor. Execution cycles are reduced by 4.1% in comparison with a core which employs previous dynamic branch predictor. ※   ()   IDEC  CAD tool  simulation  . First Author:  CAD & ES , insung78@sogang.ac.kr,  ° Corresponding Author:  CAD & ES , hwang@sogang.ac.kr,  :KICS2013-11-502, :2013 11 21, :2013 12 4, :2013 12 9 I.                / 4-Way   Element       1095           [1,2] .             .   taken           hazards   .            [3] ,      .              taken  not-taken         [4] .               ,                [5,6] .                        .       bimodal, tournament, Gshare  [3] . Bimodal    BHT (Branch History Table)          .       . Tournament  global  local              . Gshare    taken     BTAC (Branch Target Address Cache)        .              BTAC BHT  [7] .                 .                      .   4-Way BTAC MRU (Most Recently Used)   element                  .    . 2      Gshare                   .       platform  . 3  BTAC entry           MRU      .          . 4         platform  ,          .               , Gshare    ,      . 5      .

An Improved Dynamic Branch Predictor by Selective Access of a Specific Element in 4-Way Cache