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In this paper, a DFPA(decimal floating-point adder) designed a pipeline structure that uses a LZA(leading zero anticipator) to reduce critical route to shorten delay to improve the speed of operation processing. The evaluation and verification of performance of proposed DFPA applied the Flowrian tool with simulation and Cyclone III FPGA was set as the target on the Quartus II tool for the synthesis. The proposed method compared and verified to proposed the other method using same input data. As a result, the performance of proposed method is improved 11.2% and 5.9% more than L.K.Wang's method and etc.. Also, it is confirmed that improvement of operation processing speed and reduction of the number of delay elements on critical path.  :   ,   ,  ,   Key word : Decimal Floating-Point Adder, Leading Zero Anticipator, Pipeline Processing Structure, High-speed Operation Journal of the Korea Institute of Information and Communication Engineering (J. Korea Inst. Inf. Commun. Eng.) Vol. 19, No. 2 : 407~413 Feb. 2015

Design of Decimal Floating-Point Adder for High Speed Operation with Leading Zero Anticipator