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In this paper, an architecture for modified Euclidean(ME) algorithm is proposed, which is using finite-state machine(FSM) instead of degree computation. Since the proposed architecture does not have degree computation circuits, it is possible to reduce the hardware complexity of RS(Reed-Solomon) decoder, so that a very high-speed RS decoder can be implemented. RS(255,239) decoder with the proposed architecture is implemented using Verilog-HDL and requires about 13% fewer gate counts than conventional one. Key Words : Reed-Solomon, Modified Euclidean, RS decoder, FSM *  : (sjkang@kut.ac.kr) 10 3 29  10 04 26  10 06 18 1.  RS          , / ,  , ,         . ,  NAND           . RS(n,k,t)  n  (codeword) ( ), k    , ⌊⌋  RS     [1,6]. RS    1   (syndrome computation),   (Key Equation Solver, KES), Chien , Forney ,     FIFO(First Input First Output) [2-5].  KES   (error locator polynomial,

A Design of Modified Euclidean Algorithm using Finite State Machine