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This paper presents a design of the CMOS LDO regulator with a fast transient response for a high speed PMIC(power management integrated circuit). Proposed LDO regulator circuit consists of a reference voltage circuit, an error amplifier and a power transistor. 2-stage wide-band OTA buffer between error amplifier and power transistor is added for a good output stability. Although conventional source follower buffer structure is simple, it has a narrow output swing and a low S/N ratio. In this paper, we use a 2-stage wide-band OTA instead of source follower structure for a buffer. From HSPICE simulation results using a 0.5 ㎛ CMOS standard technology, simulation results were 16 mV/V line regulation and 0.007 %/mA load regulation. Key Words : PMIC, LDO Regulator, Dropout Voltage, OTA, Buffer   IDEC(IC Design Education Center)  . *  : (hjsong@inje.ac.kr) 10 01 22  10 04 02  10 04 09 1.               .           [1]. SoC         PMIC(power management integrated circuit)    [2].  PMIC    1 .     ,  (SMPS),   LDO   .           .      DC/DC .               ,   DC/DC   -      .

Design of the LDO Regulator with 2-stage wide-band OTA for High Speed PMIC