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A voltage regulator can be used to reduce the effect of the power-supply noise on the control voltage of the VCO. An accurate analysis of the voltage regulator circuit is needed for the optimal design of the voltage regulator. This paper clarifies an inaccuracy in a recent paper on the replica-compensated regulator far supply-regulated PLLs: neglect of MOSFET parasitic capacitances. As a consequence, an improved analytical model is derived for the replica-compensated voltage regulator. The derived model is verified through circuit simulation. The voltage regulator has been fabricated in a standard 1P6M CMOS technology. The chip area is .

An Analysis of n VCO Voltage Regulator for Reducing the Effect of Power Supply Noise