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Electronic devices are a ubiquitous part of today’s life. Modern electronic devices are dominated by conventional complementary metal-oxide semiconductor (CMOS) technology. Scaling of field-effect transistors (FETs) has been the key enabler for the tremendous progress in this field, in which the gate dielectric scaling is one of the most important tasks. While high-k gate dielectrics start to become part of Si technology and provide advantages over SiO2, such as smaller equivalent oxide thickness (EOT) and less gate leakage, engineering the interface between high-k materials and the Si channel has been a major obstacle and continues to be challenging. While atomic layer deposition (ALD) of high-k dielectrics is rather mature and has already been adopted by industry, a new technique, plasmaenhanced ALD (PE-ALD), is expected to open up new routes in thin film growth owing to its increased material choices, high throughput processing, and reduced growth temperatures. In this study, we focus on electrical characterization of high-k Al2O3 films deposited in a commercial PE-ALD tool, primarily using the Capacitance-Voltage (C-V) analysis. The goal is to identify optimal growth conditions. After measuring and analyzing C-V curves of Al2O3 films deposited by various conditions, the major findings are listed as follows: 1) besides the plasma assistance, 250°C growth temperature results in a higher relative permittivity and smaller hysteresis compared to lower temperatures; 2) post-growth annealing is necessary to eliminate most trapped charges. It is found that 600°C annealing most effectively reduces the hysteresis and oxide trapped charges, and is therefore the optimal annealing choice.

Synthesizing the NanoMaterials of the Future: Electrical Characterization of Aluminum Oxide Thin Film