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Microprocessors increasingly execute multiple tasks in step with the increasing complexity of modern embedded applications. Shared by multiple tasks, conventional on-chip L1 instruction cache (I-cache) usually suffers a high cache miss ratio due to inter/intra task interferences and is the most energy-consuming component of the processor chip. This paper presents a power-efficient loop instruction cache design for multitasking embedded applications, which is a two-fold technique that can significantly reduce the L1 I-cache accesses for energy saving and reduce the I-cache misses caused by task interference. Experiments on a case study show that our scheme reduces energy consumption in the I-cache hierarchy by 36.5% and I-cache misses can be reduced from 6.0% to 18.3%, depending on the frequency of context switch in the multitasking system.

A CASE STUDY OF ENERGY-EFFICIENT LOOP INSTRUCTION CACHE DESIGN FOR EMBEDDED MULTITASKING SYSTEMS