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Field programmable gate arrays (FPGAs) have become an attractive implementation medium for digital circuits. FPGA design’s big challenge is to find a good trade-off between flexibility and performance in terms of power dissipation, area density, and delay. This paper presents a new cluster-based FPGA architecture combining mesh and hierarchical interconnect topologies. Based on experimental method and benchmarks circuit implementation, this work provides a detailed exploration and analyses of the effect of cluster functionality on the proposed cluster-based FPGA in terms of power dissipation, area density, and delay. The exploration results showed that architecture with high cluster size provides high speed performance and low power dissipation. We noted also that architecture with small cluster size is more efficient in terms of area. Look-up-table (LUT) exploration showed that using architecture with 4-input LUT offers the best trade-off between power dissipation, area density, and delay.

Performance analysis and optimization of cluster-based mesh FPGA architectures: design methodology and CAD tool support