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Static power has become the most important factor in the fabrication of integrated circuits. Power gating techniques minimize leakage currents and help to develop ultra-low–power and high-performance digital circuits. In this paper, a power gating approach is proposed to minimize leakage for subnanometer technologies. Simulation results reveal that the proposed technique reduces maximum of 96% leakage power, 33% dynamic power, 49% drowsy power, and 16% energy as compared to conventional techniques. The proposed technique offers good leakage reduction, even under variation of different operating parameters.

Low leakage power gating technique for subnanometer CMOS circuits