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New way optimization method is an Enhanced CSS F2A new method titled in this paper to explain the improved flip flop design with 24 transistor’s using circuit-shared static flipflop (ECSSFlip Flop).this implementation enhances power and delay where we utilize 5 NOR gates and 2 INV's(inverters), these methods are these methods are utilized in the quality cell libraries, The ECSS FLIP FLOP utilizes a positive intercessor clock signal, it is produced from a main clock, to require information into a main latch and a negative fringe of the foundation clock to carry the info during a gated latch. Cadence(Virtuoso) simulations at 180-μm found optimized at different frequency now the ability by a power dissipation of 9.516nW and delay by 3.634 ns in comparison to CSS FLIP FLOP Keyword’s: ECSS FLIP FLOP, FLIP FLOP ( F2),

Optimization Method for Delay and Power Using Enhanced CSS FLIP FLOP with 24 Transistors