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This paper presents a fourth-order continuous-time analog filter based on the cascade of two flipped-source-follower (FSF) biquadratic (biquad) cells. The FSF biquad adopts two interacting loops (the first due to the classic source-follower, and the second to the additional gain path) which lower the impedances of all circuit nodes with relevant benefits in terms of noise power reduction and linearity enhancement. The presented device was integrated in 28 nm CMOS and featured 100 MHz −3 dB bandwidth with 67 dB Dynamic-Range. Input IP3 was 12 dBm at 10 and 11 MHz input tone frequencies. Total power consumption was 0.968 mW (0.484 mW per cell). Hence, the filter performed one of the highest figures-of-merit (160.7 dBJ-1) compared with analog state-of-the-art filters.

A 28 nm CMOS 100 MHz 67 dB-Dynamic-Range 968 µW Flipped-Source-Follower Analog Filter