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Hardware Trojan is easy to be embedded during IC’s design and manufacturing. Mostly used Trojan detection technique based on side-channel approach need a Trojan-free instance, and could not ensure Trojan-free instance’s consistent of schematic. With the help of scan chain, one of the widely used design for testability (DFT) technology, a novel approach is proposed to obtain the schematic of Application Specific Integrated Circuit (ASIC). It is verified and tested by formal verification and hardware simulation. This approach not only could help to obtain the Trojan-free instance which has the same schematic as the ordinary design, but also provide a new method to other Hardware Trojan detection techniques. Introduction The integrated circuits (IC) are vulnerable to malicious modification. For economic and time to market concerns, modern IC industry cannot avoid involving other vendors’ intellectual property(IP), electronic design automation (EDA)software tools, library, or manufacturing in other foundry. This business mode make ICs easily to be embedded Hardware Trojan. Early in 2003, the America’s whitepaper about global migration of the U.S. semiconductor industry has clearly pointed that the untrusted foundry can affect the reliability of ICs and further affect nation’s security[1]. Recent years, some side effect news has aggravated people’s worried. In the Gulf War, the U.S. army destroy Iraq’s radar by the hidden Backdoor of IC[2]. Some Europe’s IC vendors can remotely control the system to steal information or invalidate equipment by embedded Trojan[3]. For this reason, more and more research focus on the study of hardware Trojan detection. The most widely used detection methods can be classified into logic testing-based approaches and side-channel analysis-based approaches[4]. Logic testing-based approaches input test vectors to activate the Trojan and recognize its influence. Original design would be modified to improve the detecting coverage. Salmani et al propose a technique to increase the node’s toggle rate by inserting dummy flip-flop, making node’s toggle rate more than preset threshold. When threshold set as 10-4, it needs adding 16 dummy flip-flops into s38417 benchmark and 0.8% area overhead[5]. Side-channel analysis-based approaches can detect Trojan by comparing the side-channel parameter of pending test and Trojan-free ICs without triggering Trojan[4]. Side-channel analysis-based approaches has become the most widely used and effective technique[6]. Narasimhan at el use the intrinsic relationship between dynamic current and maximum operating frequency to reduce process noise’s affect, can achieve a detection resolution of 1.12 percent in±20 percent variation[7]. Side-channel analysis-based approaches need a Trojan-free IC. Agrawal et al propose a reverse-engineer method: comparing IC’s layout with original design layer by layer, if same, the testing IC will be regarded as Trojan-free IC[8]. Besides reverse-engineer’s disadvantages, this method only can ensure the testing IC’s consistency of layout rather than schematic, making this method cannot be used to detect the Trojan embedded at synthesis stage. Li Qing-bao et al propose a method to get state transition diagram base on off-line reverse analysis[9]. This method need to observe all D flip-flops’ (DFF) value from the output pins, making this method could only be applied to programmable logic device (PLD) rather than ASIC, because PLD could satisfy this feature. By matching a set of gates used to implement some function, Subramanyan et al propose a International Industrial Informatics and Computer Engineering Conference (IIICEC 2015) © 2015. The authors Published by Atlantis Press 985 method to get high level netlist with components such as register files, counter, adder, which relevant to datapath. This method can only math about 51% function and 93% logic gates[10]. The main purpose of this paper is to propose a novel method getting ASIC schematic using inherent scanchain which is original used at test stage. Firstly using scanchain, the most widely technology used in design for testability technique (DFT), divides sequential logic circuit into combinational logic block bounded by scanchain and IO ports, making it easy to get ASIC’s logic connection. Secondly this paper take formal verification technique to ensure the obtained schematic is same as the original design. Finally this paper use hardware simulation platform ensures its practicability in practical application. Theory To make it sample, this paper select small scale ASIC without RAM or ROM as the study object, which only has one scanchain with all DFFs in it. The system block diagram is shown as Fig. 1. Assuming 0 x , 1 x , ... , m 1 x − represent ASIC’s inputs, 0 y , 1 y , ... , n 1 y − represent ASIC’s outputs, 0 d , 1 d , ... , k 1 d − represent DFF’s inputs, 0 q , 1 q , ... , k 1 q − represent DFF’s outputs, SI represent scanchain’s inputs signal, SO represent scanchain’s outputs signal, SE represent test enable signal, RST_N represent reset signal. ASIC is divided into combinational logic block bounded by DFFs, inputs and outputs ports by the inherent scanchain. The ASIC’s schematic can be obtained by the following steps: first, obtain the truth table of 0 d , 1 d , ..., k 1 d − and 0 y , 1 y , ..., n 1 y − about 0 x , 1 x , ..., m 1 x − and 0 q , 1 q , ..., k 1 q − ; second, get combinational logic block’s schematic by simplifying the truth table, connect combinational logic block with scanchain and IO ports forming ASIC schematic; finally verify the obtained schematic as same as the original design with formal verification . ... ... ... COMB COMB Q Q SET

A Method of Obtaining ASIC Schematic Using Scan Chain