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In this paper, we investigate the low leakage design method for near-threshold circuits with gate-length biasing techniques. A cost-effective gate length optimization method is presented. The basic logic gates and two full adders with gate- length biasing technique are implemented and simulated using HSPICE at 45nm CMOS process. The simulation results show that the proposed gates achieved considerable leakage reduction.

Run-time Leakage Reduction in Near-threshold Circuits with Gate-length Biasing Techniques