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An 1GHz~6.25GHz phase-locked loop (PLL) for SERDES is presented in this paper. For achieving optimized balance between acquisition speed and jitter performance at all frequency points, this PLL adopts an adaptive bandwidth method. A current-programmable charge pump is introduced to make loop bandwidth configurable. And a novel Current Controller module is used to output configurable codes automatically. This PLL is implemented in 65nm, 1P10M CMOS technology, occupying an area of 0.17mm. Results show its charge pump can draw 20uA to 420uA currents from 1.2V supply, proportional to changeable bandwidth 3MHz~58MHz. The measured jitter and locking time at 6.25GHz are 5.52ps and 9.5us, respectively.

An 1GHz~6.25GHz Phase-Locked Loop for SERDES