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The technical paper discusses the reduction of high leakage current failures of semiconductor IC (integrated circuit) packages by eliminating the ESD (electrostatic discharge) events during assembly process and ensuring the appropriate machine grounding and ESD controls.  It is imperative to reduce or ideally eliminate the leakage current failures of the device to ensure the product quality, especially as the market becomes more challenging and demanding.  After implementation of the corrective and improvement actions, high leakage current occurrence was reduced from baseline of 5784 ppm to 1567 ppm, better than the six sigma goal of 4715 ppm.

Improvement on Leakage Current Performance of Semiconductor IC Packages by Eliminating ESD Events