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Adder is a building block of all arithmetic units used in processors. The performances of adders are evaluated on the basis of power consumption, energy consumption and delay. In this approach the Borrow Save Adder (BSA) is designed with minimum delay under low threshold voltage and it is compared with Ripple Carry Adder (RCA). It presents a solution for low power addition under threshold voltage variability, which successfully handles the changes of increasing threshold voltage. In addition the proposed approach demonstrates the tolerance of adder unit to variations. Keywords— Ripple Carry Adder(RCA); Borrow Save Adder(BSA); timing analysis; power consumption; threshold voltage; delay.

FPGA Implementation of Borrow Save Adder Under Threshold Voltage Variability