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This thesis dernonstrates how a behaviorai description of a circuit written in the harciware language called VHDL has been compiled into an internai representation called bdslf. This interna1 representation is based on a senes of controL/data-flow graphs to capture the behavionl aspects of the circuit. Carefd attention has been given to the proper construction of if, switch and ioop control constructs based on the behavioral descriptions from the VHDL language. Synthesis tools can be mn on the intemal representation to generare a regisrer-uansfer level description of the circuit. A graphicaî user interface was designed and constructed to display the conuol/data-flow graphs in a hierxchical tashion for the benefit of circuit and synthesis system designers. A mouse dnven browser alIows the designers to browse through the graph to any level of detail.

Generating a control/data-flow graph representation of a circuit from VHDL for use in circuit synthesis.