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The requirement of ultra low-power, area efficient and high speed analog-to-digital converters is pushing toward the use of dynamic regenerative comparators to enhance speed and power efficiency. In this paper a low power double-tail comparator proposed for 4-bit Flash Analog-to-Digital Converter by adding two transistors. The demanding issue in the design of a low power Flash ADC is the design of comparator and Thermometer code to Binary code converter at low supply voltage with low power dissipation.. The implementation of comparator and encoder is done using dynamic CMOS logic to reduce the power consumption of the Flash ADC.The encoder is MUX based thermometer to binary code converterwhich consumes 44.5365mW power. The proposed double tail comparator is designed at supply voltage of 0.8V and compared with the conventional clocked regenerative comparators having minimum power dissipation of 701.1725pW. Then, using this double tail comparator a Flash ADC having 4 bit resolution is designed which dissipates 10.0204uW power with supply voltage 1.8V. The simulation is done using Mentor Graphics back end tool with Pyxis schematic 10.5 version on LINUX operating system. KeywordsVery Large Scale Integration(VLSI), Analog to Digital Converter (ADC), Digital to Analog Converter (DAC), Complementary Metal Oxide Semiconductor(CMOS), Double Tail Comparator (DTC), Multiplexer(MUX).

Design of 4-bit Flash ADC using double tail comparator in 130nm technology