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Arithmetic calculation of complex numbers is a key part of many modern digital and optical communication systems. The multiplication of complex numbers plays a very important role in digital applications. With the use of new technologies, such as an FPGA’s, it is possible to integrate a processor, memory modules, input/output peripherals, and custom hardware accelerators into the same integrated circuit, called Systems on Programmable Chip (SoPC). This paper presents the design of a soft-core architecture used for the processing of 16-bit complex numbers. The architecture is RISC, Harvard type and has: 8-level hardware stack, 64K × 29-bit program memory, two independent bank of registers and a data memory, segmented into 2 parts to store the real and imaginary part, besides A DSP unit. We also present the results of the implementation, which was done using the VHDL hardware description language and a Xilinx FPGA. The implementation is compared with other architectures. The proposed multiplier, for the processing of integer complex arithmetic signals, has a better performance.

Procesador de números complejos enteros de alta velocidad implementada en un FPGA