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2 Department of ECE , VV College of Engineering,Tamilnadu-627657,India E-mail:n_nirmalsingh@hotmail.com Abstract: In Even Symmetric Parallel Fast Finite Impulse Response (ESPFFIR) filter adders and multipliers are the major processing elements. Multiple Constant Multipliers and low power adders reduce the area and power consumption in most of the Digital Signal Processing elements. This paper focuses on the design of ESPFFIR filter by replacing the existing Canonical Signed Digit (CSD) based Single Constant Multiplier (SCM) by Common Sub-expression Elimination (CSE) based Multiple Constant Multiplier (MCM).Carry Save Adder (CSA) is being replaced by Modified CSLA with a view to consume less power and to occupy less area. The Modified CSLA adders consume 20% less power and 15% less area than Carry Save Adder (CSA).Various CSE based algorithms like Heuristic of cumulative benefit (Hcub), n-dimensional Reduced Adder Graph (RAG-n) and Bull Horrocks Modified algorithm (BHM) have been used for designing Multiple Constant Multipliers, which are the major part in the design of ESPFFIR filter. While these algorithms are used for the design of Multiple Constant Multipliers, the CSEHcub-n use 40% less number of adders than CSD based SCM multipliers. It is understood that the CSE-Hcub-n algorithm is superior to other algorithms in designing the subfilters in the ESPFFIR filter. Here modified 12-tap 2-parallel ESPFFIR filter & 24-tap 2-parallel ESPFFIR filter have been compared together in power and area wise. The modified 12-tap 2-parallel ESPFFIR filter & 24-tap 2-parallel ESPFFIR filter consume 18% and 19.2% less area and power than the conventional design. Analysed using Cadence RC synthesize tools.

Design of Low Power and Area Efficient ESPFFIR Filter Using Multiple Constant Multiplier