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The proposed system is an efficient implementation of 16-bit MultiplierAccumulator using Radix-8 and Radix-16 Modified Booth Algorithm and seven different adders (SPST Adder, Parallel Prefix Adder, Carry Select Adder, Error Tolerant Adder, Hybrid Prefix Adder, Modified Area Efficient Carry Select Adder, Parallel Binary Adder) are using VHDL. This proposed system provides low power, high speed and less delay. The comparison between the power consumption (mw) and estimated delay (ns) of both Booth multipliers is calculated. The application of digital signal processing like fast Fourier transform, finite impulse response filters and convolution requires high speed and low power MAC (Multiplier and Accumulator) units to construct an adder. Speed of operation can be improved and dynamic power can be reduced by reducing the glitches (1 to 0 transition) and spikes ( 0 to 1 transition). The adder designed using SPST avoids the unwanted glitches and spikes, minimizing the switching power dissipation and hence the dynamic power. The speed can be improved by reducing the number of partial products to half by grouping of bits from the multiplier term. The proposed Radix-8and Radix-16 Modified Booth Algorithm MAC with SPST reduces the delay with less power consumption as compared to array MAC.

Fast Computation Using High Radix Signed Digit Number with Different Adders