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Serial input data is multiplied with constant pair to produce constant multiplication called Multiple Constant Multiplications (MCM). In order to reduce number of shifting, an addition/subtraction operation, Graph Based (GB) algorithm is taken as a proposed algorithm to construct multiplier for transposed form of digit serial FIR (Finite Impulse Response) filter design 4-tap digit serial FIR filter with digit size d=2,4,8. To analyze low complexity Digit based recoding algorithm and CSE (Common Subexpression Elimination) algorithm simulation compared with GB algorithm based on the performance of area utilization and delay report in Xilinx ise design suite12.1software. Finally this FIR filter is implemented in FPGA spartan3 hardware for real time implementation.

LOW COMPLEXITY DIGIT SERIAL FIR FILTER BY MULTIPLE CONSTANT MULTIPLICATION ALGORITHMS