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This paper presents a novel architecture to achieve a low power and small area pipelined SAR-ADC which used in a CMOS image sensor. The sub-SAR ADC is a key module to lower power consumption and design complexity. The high-resolution first stage, the half-gain MDAC and the dynamic comparator are adopted to improve the linearity and to reduce the power. This pipelined SAR ADC is fabricated in 180nm CMOS technology with active area of only 140um×280um. The ADC achieves 60.37dB signal-to-noise and distortion ratio (SNDR) and 76.37dB spurious free dynamic range (SFDR) with 3MHz frequency input. The power dissipation is 9.8mW in typical case under 2.8V supply.

A 10Bit Small Area Low Power Pipelined SAR ADC Used in CMOS Image Sensor