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Stencil computation is one of the most widely-used compute patterns in highperformance computing applications. Spatial and temporal blocking have beenproposed to overcome the memory-bound nature of this type of computation bymoving memory pressure from external memory to on-chip memory on GPUs. However,correctly implementing those optimizations while considering the complexity ofthe architecture and memory hierarchy of GPUs to achieve high performance isdifficult. We propose AN5D, an automated stencil framework which is capable ofautomatically transforming and optimizing stencil patterns in a given C sourcecode, and generating corresponding CUDA code. Parameter tuning in our frameworkis guided by our performance model. Our novel optimization strategy reducesshared memory and register pressure in comparison to existing implementations,allowing performance scaling up to a temporal blocking degree of 10. We achievethe highest performance reported so far for all evaluated stencil benchmarks onthe state-of-the-art Tesla V100 GPU.

AN5D: Automated Stencil Framework for High-Degree Temporal Blocking on GPUs