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The ongoing shrinking of interconnects in integrated circuits (ICs) induces reliability issues caused by electromigration (EM), including void-induced failure mechanisms in IC vias. We propose a new post-routing approach to insert redundant vias specially targeted for EM avoidance. Our algorithm compares all possible insertions and utilizes the configuration with the highest reliability gain. This is achieved by considering the connecting segment loads. These loads are an estimation of the risk involved in creating EM-induced voids as a continuous function of current density, segment length and stress development over time. Inserting vias in those segments with highest loads, our approach efficiently increases circuit reliability by reducing EM effects. We were able to reduce the total, average and maximum via load for the MCNC benchmark suite on average by 6.6%, 4% and 13.9%, respectively. The increase in via reliability was confirmed by subsequent modeling of EM-inducing factors.

Load-Aware Redundant Via Insertion for Electromigration Avoidance