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This paper describes enhancements and applications of the SimpleScalar simulator for undergraduate and graduate courses on computer architecture. The enhancements include additional instruction profiling statistics, visualization of data hazards, visualization of memory access behavior, and multiprocessor capabilities with visualization of cache coherence. The applications include prediction of pipelined execution time with stalls for hazards and cache misses, instilling deeper insight into cache locality, parallel programming, and a greater appreciation of cache coherence interactions for multiprocessor programs.

Enhancements and applications of the SimpleScalar simulator for undergraduate and graduate computer architecture education