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The charge-trapping memory devices namely Pt/Al 2 O 3 /(Al 2 O[Formula: see text](Cu 2 O)[Formula: see text]/SiO 2 /[Formula: see text]-Si with 2, 3 and 4 nm SiO 2  tunneling layers were fabricated by using RF magnetron sputtering and atomic layer deposition techniques. At an applied voltage of ±11 V, the memory windows in the C–V curves of the memory devices with 2, 3 and 4 nm SiO 2  tunneling layers were about 4.18, 9.91 and 11.33 V, respectively. The anomaly in memory properties among the three memory devices was ascribed to the different back tunneling probabilities of trapped electrons in the charge-trapping dielectric (Al 2 O[Formula: see text](Cu 2 O)[Formula: see text] due to the different thicknesses of SiO 2  tunneling layer.

The effect of the thickness of tunneling layer on the memory properties of (Cu2O)0.5(Al2O3)0.5 high-k composite charge-trapping memory devices