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In this article, we present a low-power (LP) anomaly detection integrated circuit (ADIC) based on a one-class classifier (OCC) neural network. The ADIC achieves LP operation through a combination of: 1) careful choice of algorithm for online learning and 2) approximate computing techniques to lower average energy. In particular, online pseudoinverse update method (OPIUM) is used to train a randomized neural network for quick and resource-efficient learning. An additional 42&#x0025; energy saving can be achieved when a lighter version of OPIUM method is used for training with the same number of data samples lead to no significant compromise on the quality of inference. Instead of a single classifier with large number of neurons, an ensemble of <inline-formula> <tex-math notation="LaTeX">$K$ </tex-math></inline-formula> base learner (BL) approach is chosen to reduce learning memory by a factor of <inline-formula> <tex-math notation="LaTeX">$K$ </tex-math></inline-formula>. This also enables approximate computing by dynamically varying the neural network size based on anomaly detection. Fabricated in 65-nm CMOS, the ADIC has <inline-formula> <tex-math notation="LaTeX">$K=7$ </tex-math></inline-formula> BLs with 32 neurons in each BL and dissipates 11.87 and 3.35 pJ/OP during learning and inference, respectively, at <inline-formula> <tex-math notation="LaTeX">$V_{\text {dd}}=0.75\,\,\text {V}$ </tex-math></inline-formula> when all seven BLs are enabled. Furthermore, evaluated on the NASA bearing data set, approximately 80&#x0025; of the chip can be shut down for 99&#x0025; of the lifetime leading to an energy efficiency of 0.48 pJ/OP, an <inline-formula> <tex-math notation="LaTeX">$18.5 \times $ </tex-math></inline-formula> reduction over full-precision computing running at <inline-formula> <tex-math notation="LaTeX">$V_{\text {dd}}=1.2 \,\, \text {V}$ </tex-math></inline-formula> throughout the lifetime.

ADIC: Anomaly Detection Integrated Circuit in 65-nm CMOS Utilizing Approximate Computing