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We present the design and the test results of a dual-channel Vertical-CavitySurface-Emitting Laser (VCSEL) driver ASIC LOCld65 for detector front-endreadout. LOCld65 is designed in a commercial 65-nm CMOS technology with a powersupply of 1.2 V. LOCld65 contains two separate channels with the same structureand the two channels share an I2C slave. Each channel consists of an inputamplifier, four stages of limiting amplifiers (LAs), a high-current outputdriver, and a bias-current generator. In order to extend the bandwidth, theinput amplifier uses an inductive peaking technique and the LAs use a sharedinductive peaking technique. The input amplifier and the output driver eachutilize a Continuous-Time Linear Equalizer (CTLE). The LAs employ activefeedback. The modulation current, the bias current, the peaking strength of theCTLEs, and the feedback strength of LAs are programmable through an I2Cinterface. In order to protect from the radiation damage, the I2C slave isimplemented with triple modular redundancy. Each channel of LOCld65 is testedto operate up to 14 Gbps with typical power dissipations (the VCSEL included)of 68.3 mW/channel and 62.1 mW/channel at the VCSEL voltages of 3.3 V and 2.5V, respectively. LOCld65 survives 4.9 kGy(SiO2). LOCld65 is an excellent matchfor the serializer-deserializer ASIC lpGBT in single- or dual-channel opticaltransmitters in HL-LHC upgrade applications.

LOCld65, A Dual-Channel VCSEL Driver ASIC For Detector Front-End Readout