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A capacitive DAC is an important building block of a charge-redistribution SAR ADC, for its size has a significant impact on performance. For medium- to high-resolution applications, the size of the DAC is typically determined by random mismatches. As such, an effective mismatch calibration circuit can allow the DAC to be scaled down to a much lower <i>kT/C</i> noise limit, thereby increasing the overall ADC power efficiency. This paper reviews some of the most important reported mismatch calibration techniques and proposes a foreground calibration method based on a deterministic self-calibration and stochastic quantization. This approach is experimentally validated on a prototype 10-bit SAR ADC fabricated in TSMC 28-nm LP CMOS technology, demonstrating an INL and SFDR improvement of respectively 6.4 LSB and 14.9 dB at 85 MS/s.

A Mismatch Calibration Technique for SAR ADCs Based on Deterministic Self-Calibration and Stochastic Quantization