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The human brain has something very special about energy efficiency. This is the key rationale behind the current surge of interest in neuromorphic computing. In this domain, Spiking Neural Networks are the preferred model of computation because of the high degree of sparseness in their activity in both space and time, which holds promise of ultra-low power, fast and event-driven information processing. Asynchronous realizations of neuromorphic systems are the best match with their event-driven model of computation (and communication!), since spikes can be generated, routed and consumed in an event-driven manner with maximal activity gating during idle periods. Most large-scale neuromorphic computing systems use networks-on-chip (NoCs) as communication fabric for their massively-parallel neurosynaptic framework. However, not all of them (especially academic ones) are asynchronous, since design methods and tools for asynchronous NoC design are still far from consolidated, lack optimality and/or flexibility, and are not available for the research community at large. In the best case, when asynchronous NoCs are deployed (especially in industry-driven prototypes), they seem to have been force-fitted into the new environment, since their design goals are at odds with the ultra-low power requirements of neuromorphic computing. This keynote will review state-of-the-art in large-scale neuromorphic computing systems, highlight their massive connectivity requirements and the pivotal role that interconnect technologies play to bring scalability and power efficiency to the next step. Along this direction, it will present a promising asynchronous interconnect technology combining synchronous-equivalent design flexibility with ultra-low energy-per-bit and area footprint, which lays the groundwork for asynchronous NoCs better suited for use as neuromorphic hardware.

Keynote Talk: Ultra-Low Power and Flexible Asynchronous Interconnect Technology for Large-Scale Neuromorphic Computing