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Cryogenic CMOS is a crucial component in building scalable quantum computers, predominantly for interface and control circuitry. Further, high-performance computing can also benefit from cryogenic boosters. This necessitates an in-depth understanding of the power and performance trade-offs in the cryogenic operation of digital logic. In this article, we analyze digital standard cells in a 28 nm high-<inline-formula> <tex-math notation="LaTeX">$k$ </tex-math></inline-formula> metal gate (HKMG) CMOS foundry process design kit (PDK). We have developed Berkeley Short-channel IGFET Model (BSIM)4 of cryogenic CMOS and calibrated them with experimental measurements. Since low-temperature operation leads to an exponential decrease in the leakage current of the transistors, we further tune the threshold voltage of the devices to achieve iso-leakage. In this article, we present inverter static and dynamic characteristics and multiple ring oscillator (RO) structures. The simulation study shows that we can achieve 28&#x0025; (FO4-RO) &#x2013; 59&#x0025; (NAND3-RO) higher performance under iso-<inline-formula> <tex-math notation="LaTeX">$V_{\mathrm {DD}}$ </tex-math></inline-formula> scenario and up to 90&#x0025; improvement in the energy-delay product (EDP) under iso-overdrive scenario at 6 K compared to room temperature.

Power Performance Analysis of Digital Standard Cells for 28 nm Bulk CMOS at Cryogenic Temperature Using BSIM Models