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This article presents a millimeter-wave (mmW) frequency synthesizer based on a new charge-sharing locking (CSL) technique. A charge-preset capacitor is introduced for charge sharing with a resonant <italic>LC</italic>-tank for phase correction, while the resulting charge residue on the sharing capacitor is processed by a digital frequency-tracking loop (FTL) against the process, voltage, and temperature (PVT) variations. Furthermore, a general phase noise (PN) theory of CSL, with injection locking (IL) being a special case, is proposed based on a unified multirate <inline-formula> <tex-math notation="LaTeX">${z}$ </tex-math></inline-formula>-domain model, supporting any frequency division ratio <inline-formula> <tex-math notation="LaTeX">${N}$ </tex-math></inline-formula> and CSL (or IL) strength <inline-formula> <tex-math notation="LaTeX">$\beta $ </tex-math></inline-formula>. The new theory sheds light not only on all IL-like PN phenomena (chiefly, its &#x201C;loop&#x201D; bandwidth being up to half of the reference frequency, and the oscillator PN increasing 3 dB beyond the &#x201C;loop&#x201D; cutoff frequency) but also on how to choose the CSL bandwidth via the sharing capacitor in order to optimize the rms jitter performance. The prototype in 28-nm CMOS achieves 77-fs rms jitter in 21.75&#x2014;26.25 GHz while consuming 16.5 mW for mmW quadrature frequency generation.

A Charge-Sharing Locking Technique With a General Phase Noise Theory of Injection Locking