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In highly scaled MOSFETs, random telegraph noise (RTN) can decrease the reliability and yield of circuits. RTN is produced by charge trapping, which in large devices results in <inline-formula> <tex-math notation="LaTeX">$1/f$ </tex-math></inline-formula> noise. We derived analytical formulations for modeling the impact of RTN in the delay of inverters and in the jitter of ring oscillators. We show that the parameters of interest when characterizing RTN for circuit analysis are the distribution of current deviations and the density of traps in the space of area, energy and in log-space of time-constants. The model gives a direct relation between jitter variance in oscillators (or delay variance in inverters) and the power spectral density of RTN, which includes <inline-formula> <tex-math notation="LaTeX">$1/f$ </tex-math></inline-formula> noise. The formulations can be written using time- or frequency-domain parameters.

Random Telegraph Noise Modeling for Circuit Analysis: RTN in Ring Oscillators