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In this paper, the SiC planar MOSFET with built-in reverse MOS-channel diode (SiC MCD-MOSFET) is investigated utilizing TCAD simulation tools. When the device is working as a freewheeling diode, the operation of the parasitic body diode is suppressed effectively due to the lower threshold voltage of the MCD. Therefore, the bipolar degradation issue can be completely solved. In addition, the SiC MCD-MOSFET is featuring superior dynamic characteristics. The input capacitance (<inline-formula> <tex-math notation="LaTeX">${C} _{\mathrm{ ISS}}$ </tex-math></inline-formula>), reverse transfer capacitance (<inline-formula> <tex-math notation="LaTeX">${C} _{\mathrm{ RSS}}$ </tex-math></inline-formula>), gate charge (<inline-formula> <tex-math notation="LaTeX">${Q} _{\mathrm{ G}}$ </tex-math></inline-formula>) and gate-to-drain charge (<inline-formula> <tex-math notation="LaTeX">${Q} _{\mathrm{ GD}}$ </tex-math></inline-formula>) are reduced by a factor of &#x007E;2, &#x007E;7, &#x007E;2 and &#x007E;10, respectively, as compared to the conventional SiC MOSFET (SiC C-MOSFET). Combined with the slightly increased on-resistance (<inline-formula> <tex-math notation="LaTeX">${R} _{\mathrm{ ON}}$ </tex-math></inline-formula>), tremendously enhanced figures of merit (<inline-formula> <tex-math notation="LaTeX">${R} _{\mathrm{ ON}} \times {Q}_{\mathrm{ G}}$ </tex-math></inline-formula> and <inline-formula> <tex-math notation="LaTeX">${R} _{\mathrm{ ON}} \times {Q}_{\mathrm{ GD}}$ </tex-math></inline-formula> are decreased by a factor of 1.8 and 9, respectively) are obtained in the SiC MCD-MOSFET. The outstanding performance and easy-to-implement feature make the SiC MCD-MOSFET more attractive for further power electronic applications.

SiC Planar MOSFETs With Built-In Reverse MOS-Channel Diode for Enhanced Performance