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This paper proposes a Silicon Carbide (SiC) based planar junctionless transistor (JLT), designed and simulated for low to medium power electronic applications, with a calibrated deck of SiC parameters. The simple structure of this device avoids the fabrication complexity associated with intricate junction geometries of vertical power devices and growth challenges of lateral heterostructure ones. Because of the wide bandgap (WBG) of SiC, the device exhibits a breakdown voltage of 100 V at channel length of 0.1  μ m, which may be enhanced, at the cost of operating speed, by increasing the channel length. Compared to commercial enhancement-mode GaN (e-GaN) devices with similar breakdown voltage specification, the proposed device offers lower specific on-resistance ( R on , sp ), and a significant reduction in capacitance due to its naturally self-aligned structure, leading to higher operating speed concluded from the mixed-mode simulations.

Silicon carbide planar junctionless transistor for low-medium voltage power electronics