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Adiabatic quantum-flux-parametron (AQFP) logic is an energy-efficientsuperconductor logic family. The latency of AQFP circuits is relatively longcompared to that of other superconductor logic families and thus such circuitsrequire low-latency clocking schemes. In a previous study, we proposed alow-latency clocking scheme called delay-line clocking, in which the latencyfor each logic operation is determined by the propagation delay of theexcitation current, and demonstrated a simple AQFP buffer chain that adoptsdelay-line clocking. However, it is unclear whether more complex AQFP circuitscan adopt delay-line clocking. In the present study, we demonstrate AQFP logicgates (AND and XOR gates) that use delay-line clocking as a step towardsimplementing large-scale AQFP circuits with delay-line clocking. AND and XORgates with a latency of approximately 20 ps per gate are shown to operate at upto 5 and 4 GHz, respectively, in experiments. We also demonstrate thatdelay-line clocking enables phase skipping operation, in which some of the AQFPbuffers for phase synchronization are removed to reduce the junction count andenergy dissipation. The results indicate that delay-line clocking can enablelow-latency, low-energy, large-scale AQFP circuits.

Adiabatic quantum-flux-parametron with delay-line clocking: logic gate demonstration and phase skipping operation