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Three-dimensional (3D) integration based on through-silicon-via (TSV) is an emerging technology. It provides reduced interconnection length, heterogeneous integration, higher performance, and bandwidth. However, 3D design poses several challenges and testing of 3D integrated circuits (ICs) is a key challenge. So, effective test mechanisms are necessary to test this new generation chip. In this paper, we address test architecture optimization and test schedule for 3D System-on-Chip (SoC). A novel heuristic is suggested to minimize the post-bond test time of 3D SoC under the constraints of TSV and power consumption. Also, the total test time is minimized by considering the routing cost of test access mechanisms (TAMs). We minimize the TAM wire length by sharing TAM segments in pre-bond tests and post-bond test. Simulations are carried out on different ITC'02 test benchmarks that demonstrate the efficiency of the proposed method.

Test Architecture Optimization for Post-bond Test and Pre-bond Tests of 3D SoCs Using TAM Reuse