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Power consumption issues in VLSI circuits resulted in the emergence of promising technologies – like reversible computing. The introduction of such computing paradigm has turned out to be beneficial for the application of low power CMOS design, communications and in the emerging area of quantum computing. With these benefits, physical realization of reversible circuits has received significant attention in the semiconductor industry. Additionally, to make a robust implementation of this technology, testing has been considered an essential component and several works on this filed are being reported on a daily basis. Although, many works on the efficient detection of gate faults exist but our main focus is not only to detect the faults in the circuit but also to localize the fault with 100% accuracy. Considering this aspect, in this article we propose a fault detection and localization scheme for the existing missing gate fault models in reversible circuits. In our approach, initially test vectors ( T ) are computed and then an algorithm executes to generate a unique test set ( U ). Once the test set ( U ) is generated, it is applied to detect any type of faults if exist in the circuit. Our approach has been successfully tested for all types of missing gate faults –  SMGF ,  PMGF  and  MMGF . In way to verify the functional correctness of our scheme, we also have executed the testing policy over a wide spectrum of benchmarks and experimental findings are cross checked. The obtained results have been compared with peer-reviewed works and improvements are reported.

An Approach for Detection and Localization of Missing Gate Faults in Reversible Circuit