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In todays world, high-power computing applications such as image processing,digital signal processing, graphics, and robotics require enormous computingpower. These applications use matrix operations, especially matrixmultiplication. Multiplication operations require a lot of computational timeand are also complex in design. We can use field-programmable gate arrays aslow-cost hardware accelerators along with a low-cost general-purpose processorinstead of a high-cost application-specific processor for such applications. Inthis work, we employ an efficient Strassens algorithm for matrix multiplicationand a highly efficient run-time-reconfigurable floating-point multiplier formatrix element multiplication. The run-time-reconfigurable floating-pointmultiplier is implemented with custom floating-point format forvariable-precision applications. A very efficient combination of Karatsubaalgorithm and Urdhva Tiryagbhyam algorithm is used to implement the binarymultiplier. This design can effectively adjust the power and delay requirementsaccording to different accuracy requirements by reconfiguring itself during runtime.

Run-Time-Reconfigurable Multi-Precision Floating-Point Matrix Multiplier Intellectual Property Core on FPGA