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Formal based synthesis allows design space exploration to identify optimized implementations conforming to the initial abstract specification. Wepropose to exploit the synergies between formal synthesis (at high level of abstraction) and logic synthesis (at lower levels of abstraction). In this way a two-fold goal is reached: quantitative figures are provided as a measureof the applicability of formal reasoning in the design process, and the good integration of the two phases in a unified design flow is demonstrated. Users' benefits include both improved quality of the design process (reduced time-to-market) and improved reliability of the final products (increased competitive profile).

Quantitative evaluation of formal based synthesis in ASIC design